The present application relates to a pattern formation method, and more particularly to integration of densely packed semiconductor fins formed by a directed self-assembly (DSA) process and semi-isolated semiconductor fins formed by a sidewall image transfer (SIT) process on a single substrate.
Directed self-assembly (DSA) is a patterning technique that generates sub-lithographic line/space patterns through microphase separation of a block copolymer. The DSA process has shown promise in creating large areas of patterned lines with a minimum pitch equal to a natural period (i.e., pitch) of the block copolymer, and thus is suitable for making dense fin field effect transistors (FinFETs) in a logic area of an integrated circuit. However, the DSA process does not allow for forming patterned lines with a minimum pitch that is 1.5× the natural pitch of the block copolymer; since defects will occur within the DSA pattern. Since the pitch of patterned features determines the size of static random access memory (SRAM) cells and the minimum pitch in a SRAM area of the integrated circuit that is equal to 1.5× the natural pitch of the DSA material is desired to achieve high SRAM cell density, methods of forming nanoscale features with desirable pitches for both logic and SRAM devices remain needed.